1. Field of the Invention
This invention relates generally to analog-to-digital converter (ADC) circuitry, primarily of the pipelined architecture, and more specifically to a new nested pipelined architecture for this type circuit.
2. Brief Description of the Prior Art
A block diagram of the architecture for a conventional multi-bit per stage pipelined Analog-to-Digital Converter (ADC) is shown in FIG. 1. The total number of bits is broken into K stages 1-5, sometimes with an equal number of bits per stage but not necessarily so. An analog input voltage signal V.sub.IN is applied to the first stage 1, with the output of each stage k being coupled to the following stage k+1 in a pipeline fashion. Each stage is comprised of the circuitry shown in the block diagram in blow-up 6 of exemplary stage 2.
In operation, the analog input voltage signal V.sub.IN is first sampled by a Sample-and-Hold Amplifier (SHA) 7. This sampled signal is then quantized by a multi-bit Analog-to-Digital sub-Converter (ADSC) 8, converted back to an analog voltage using a Digital-to-Analog sub-Converter (DASC) 9, and then subtracted from the sampled input by a difference circuit 10. For each stage k, the resulting difference signal, known as the residue, is then multiplied by a factor of 2.sup.m, where m is the number of bits resolved in the stage, by an amplifier 11 to bring the signal back to full scale value. The amplified residue signal V.sub.RESk is then presented to the next stage k+1 of the pipeline where a similar set of operations is performed.
At each stage a digital output for the m-bits is present at the output of the ADSC 8. After the signal propagates through the K stages, a digital representation of the input signal V.sub.IN is provided by the concatenation of the multi-bit digital outputs from the ADSC 8 of each stage k. In a typical design, the ADSC 8 is a flash converter, while the DASC 9 is a switched capacitor multiplying DAC.
It is commonly known in the art that increasing the number of bits per stage in a pipelined ADC relaxes the capacitor matching requirements and enhances the achievable resolution of the overall ADC, but it also increases the number of comparators and resistors in the ADSC 8 circuit as well as the comparator offset voltage requirements. In a conventional ADC, additional circuitry and power must be utilized to reduce this offset voltage to an acceptable level. Also, the additional number of comparators required when the number of bits is increased, places more load on the operational amplifier, resulting in slower operation of the overall circuitry.
FIG. 2a shows a 1-bit/stage implementation for a typical switched capacitor circuit which uses the same components in both sampling and amplification phases. The circuit is comprised of capacitors C1 and C2 (12 & 13), an operational amplifier 14, a comparator 15, and switches 16-19, which are controlled by the alternating phases of clock signals. Under control of the clock signals, the positions of the switches 16-19 alternate between a sampling configuration and an amplification configuration, as illustrated by the clock cycles shown in the signal timing diagram of FIG. 2b. In FIG. 2a, the switch positions during the sampling phase are shown by a solid line, while the switch positions during the amplification phase are shown by a dashed line.
FIGS. 3a and 3b show a typical implementation of a stage k of a pipelined ADC which includes a sampling phase, as shown in FIG. 3a, and an amplification phase, as shown in FIG. 3b, These circuits are based on the circuit shown in FIG. 2a, and are configured using the switches discussed above in connection with FIGS. 2a and 2b. For simplicity, this discussion in limited to 1-bit/stage. The voltage of the input signal V.sub.IN, or, alternatively, V.sub.RESk-1, is first sampled on capacitors C1 (12) and C2 (13) during the sampling phase as shown in FIG. 3a. A single comparator 15 is used to determine if V.sub.IN is greater than or less than half of the full scale voltage, which in this case is 0 volts. For this one bit per stage example, comparator 15 is used as the ADSC, although in multi-bit/stage implementations the ADSC is typically a flash converter. Depending on the comparator 15 decision, d, the bottom plate of C2 (13) is connected to either +V.sub.REF or -V.sub.REF during the amplification phase, as shown in the following Table 1:
TABLE 1 V.sub.IN d Select &lt;0 0 -V.sub.REF &gt;0 1 +V.sub.REF
At the same time, the bottom plate of C1 (12) is connected to the output of operational amplifier 14, as shown in FIG. 3b, Since the input of operational amplifier 14 is a high impedance node, the charge stored at the instant when the sampling occurs remains unchanged during the amplification phase. By applying this charge conservation principle, it can be shown that the output V.sub.RESk of the operational amplifier 14, also known as the residue, is given by: ##EQU1##
In the case where C1 and C2 are perfectly matched, these equations reduce to: EQU V.sub.RESk =2*V.sub.IN +V.sub.REF, if d=0, i.e., V.sub.IN &lt;0 EQU V.sub.RESk =2*V.sub.IN -V.sub.REF, if d=1, i.e., V.sub.IN &gt;0.
FIGS. 4a and 4b show the typical circuits for a multi-bit/stage implementation of a pipelined ADC. The circuits look much like the one bit per stage circuits, discussed above, but with additional components. FIGS. 4a and 4b show multi-bit/stage implementations for the sampling and amplification circuitry, respectively. These circuits require 2.sup.m capacitors; i.e., for the two bit per stage example shown there are 2.sup.2 =4 capacitors 12-13 and 20-21. Also, for this two bit per stage circuit the ADSC is a two bit flash converter 22. FIG. 4c is the circuit for a multi-bit/stage ADSC circuit 22. The circuit consists of a stack of 2.sup.m resistors 23-26, 2.sup.m -1 comparators 27-29, and some encoding logic circuitry 30 to provide the digital output. Although the flash converter is fast, it requires a considerable amount of circuitry when m is large. Additional drawbacks are that the hardware, power, and component area all grow exponentially with the number of bits and the circuit requires precision comparators and resistors.
Typically, digital error correction is used to overcome the effects of off-set voltage in the comparators used in the ADSC. With digital error correction the amplitude of the V.sub.IN voltage is attenuated by a factor of 2 to ensure that the operational amplifiers do not saturate. Also, the digital output from the ADSC must be multiplied by two, but this is easily accomplished by shifting the digital word one bit to the left. This shift does cause a one-bit overlap in the concatenated word from the two stages which somewhat reduces the efficiency in parts count in multi-bit per stage implementations.
In the past, single-bit per stage pipelined ADCs have been used because of their simplicity but with today's requirements for twelve to sixteen bit resolution in applications such as digital signal processing (DSP) and others, multi-bit/stage implementations are often required. The multi-bit/stage architecture has relaxed component matching requirements. However, because of increased complexity in the ADSC, current pipelined ADC implementations are limited to about five bits per stage.
Accordingly, it is an object of the present invention to provide a pipelined ADC architecture allowing implementation beyond five bits. It is another object of the present invention to provide a pipelined ADC having a more efficient use of constituent circuit components, such as comparators, capacitors and resistors. It is a still further object of the present invention to provide a pipelined ADC architecture that permits relaxing the capacitor matching requirements in the circuits thereof.